| INVITED SPEECH | ||
 | Nino Stojadinovic - University of Nis, Serbia NBTI and Radiation Related Degradation and Lifetime Estimation in Power VDMOSFETs | |
| Abstract | ||
| Threshold voltage shifts associated with NBT (Negative Bias Temperature) instability in power VDMOSFETs under the static and pulsed stress conditions are analyzed in terms of the effects on device lifetime. For that purpose, the method suitable for performing fast NBT instability measurements on power VDMOSFETs is proposed, and its practical implementation using a simple boosting circuit for obtaining required gate stress voltage, and sweep I-V measurements for the threshold voltage shift determination will be presented. Experimental results will be discussed in terms of time necessary to perform interim measurements during NBT stress tests, and it will be shown that the measurements could be done fast enough to intercept dynamic recovery effect in these devices. It should be emphasized that the pulsed bias stressing is found to cause less significant threshold voltage shifts in comparison with those caused by the static stressing.. Accordingly, pulsed gate bias conditions provide much longer device lifetime than the static ones, which is shown by the individual use of the 1/VG and 1/T models for extrapolation to normal operating voltage and temperature, as well as by combined use of both models for a double extrapolation successively along both voltage and temperature axes. A double extrapolation approach is shown to allow for the construction of the surface area representing the lifetime values corresponding to a full range of device operating voltages and temperatures. The results of consecutive irradiation and NBT stress experiments performed on power VDMOSFETs will be also presented. It is shown that irradiation of previously NBT stressed devices leads to further increase of threshold voltage shift, while NBT stress effects in previously irradiated devices may depend on gate bias applied during irradiation and on the total dose received. In the case of low-dose irradiation or irradiation without gate bias, the subsequent NBT stress seems to lead to further device degradation, whereas in the case of devices previously irradiated to high doses or with gate bias applied during irradiation, NBT stress seems to have a positive role as it practically anneals a part of radiation-induced degradation. | ||
| Biography | ||
| Ninoslav D. Stojadinović (M’86-SM’98-F’03) received B.S. (1974), M.S. (1977) and Ph.D. (1980) degrees, all in electrical engineering, at the Faculty of Electronic Engineering, University of Niš, Serbia, where he was professor at the Department of Microelectronics, Faculty Dean (1989-1994) and Department Head (1985-2005). He is member of Serbian Academy of Sciences and Arts (2003), and Academy of Engineering Sciences of Serbia (1000). His research interest includes semiconductor device physics and modeling and device reliability and failure physics. He has authored or coauthored over 300 papers in the international journals and conference proceedings, and supervised 15 Ph.D theses. He is IEEE ED/SSC Serbia&Montenegro Chapter Chair, IEEE EDS Distinguished Lecturer (since 1997), Chairman of IEEE International Conference on Microelectronics – MIEL (since 2002), and Editor-in-Chief of Facta Universitatis: Electronics and Energetics (since 2013). He was Editor-in-Chief of Microelectronics Journal (1993-1996), IEEE EDS Newsletter (2002-2013), and Microelectronics Reliability (1996-2017). | ||
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